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Cache memory
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#	Item
941	Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA. Add to Reading List Source URL: www.markrtuttle.com Language: English - Date: 2007-04-26 00:00:00 Theoretical computer science Instruction set architectures Computer memory Parallel computing Cache coherency Model checking CPU cache Formal verification Communications protocol Computing Computer architecture Computer hardware
942	DeNovoND: Efficient Hardware Support for Disciplined Non-Determinism Hyojin Sung, Rakesh Komuravelli, and Sarita V. Adve Department of Computer Science University of Illinois at Urbana-Champaign {sung12, komurav1, sadve} Add to Reading List Source URL: rsim.cs.illinois.edu Language: English - Date: 2013-02-13 15:41:56 Concurrent computing Transaction processing Computer memory CPU cache Central processing unit MESI protocol Lock Cache Linearizability Computing Cache coherency Concurrency control
943	Imagination_Guidelines_20Feb13.indd Add to Reading List Source URL: www.imgtec.com Language: English - Date: 2014-02-20 08:23:14 Instruction set architectures Computer engineering Embedded systems Microcontrollers MIPS architecture Memory management unit Motorola 68000 family Instruction set CPU cache Computer architecture Computer hardware Central processing unit
944	MIPS32® 1004K™ Coherent Processing System (CPS) MIPS32 1004K™ ® multiprocessor IP Add to Reading List Source URL: www.imgtec.com Language: English - Date: 2013-07-17 06:19:48 Microprocessors Instruction set architectures Computer memory MIPS Technologies MIPS architecture CPU cache Multi-core processor Cache Loongson Computer architecture Computing Computer hardware
945	Presented at the 12th Symposium on Computer Architecture and High-Performance Computing, October[removed]Efficient ECC-Based Directory Implementations for Scalable Multiprocessors Kourosh Gharachorloo, Luiz André Barroso Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:37:55 Digital media CPU cache Dynamic random-access memory Synchronous dynamic random-access memory SGI Origin Random-access memory Cache Memory bandwidth Memory hierarchy Computer memory Computer hardware Computing
946	Barrelfish Project ETH Zurich Barrelfish on the Intel Single-chip Cloud Computer Barrelfish Technical Note 005 Add to Reading List Source URL: www.barrelfish.org Language: English - Date: 2013-12-13 09:57:02 Cloud computing Single-chip Cloud Computer Computer memory Monolithic kernels Virtual memory CPU cache Operating system Paging Kernel Computer architecture Computing Software
947	Appeared in the Proceedings of the 20th Intl. Symp. on Computer Architecture, May[removed]The Performance of Cache-Coherent Ring-based Multiprocessors Luiz André Barroso and Michel Dubois [removed]; dubois@par Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:37:39 Parallel computing CPU cache Cache Central processing unit Scalable Coherent Interface Bus sniffing Computing Cache coherency Computer memory
948	PowerPoint プレゼンテーション Add to Reading List Source URL: www.hpc.is.uec.ac.jp Language: English - Date: 2006-10-18 00:00:30 Computer hardware Computer architecture Cache Computer memory Supercomputer CPU cache Vector processor R8000 Computing Parallel computing Central processing unit
949	Master’s Thesis Nr. 89 Systems Group, Department of Computer Science, ETH Zurich NUMA Migration on the Barrelfish OS by Add to Reading List Source URL: www.barrelfish.org Language: English - Date: 2013-11-27 05:09:13 Non-Uniform Memory Access Uniform memory access C dynamic memory allocation Cache-only memory architecture Parallel database Parallel computing Computing Computer memory
950	Appeared in Proceedings of the 25th Annual International Symposium on Computer Architecture, June[removed]An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors Jack L. Lo, Luiz André Barro Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:36:19 Central processing unit Threads Computer memory Parallel computing CPU cache Simultaneous multithreading Multithreading Cache Translation lookaside buffer Computer hardware Computing Computer architecture

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